indus t rial po wer c o ntrol eic e dr iv er ? co m pac t high voltage gate driver ic final dat a s heet , 01.06.2016 final 2e dl fa mi ly 600 v half bridge gate drive ic 2EDL05I06PF 2edl05i06pj 2edl05i06bf 2edl05n06pf 2edl05n06pj eicedriver? compact
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eicedriver? compact 2e dl family final datasheet 3 , 01.06.2016 revision history page or item su bjects (major changes since previous revision) , 16.04.2013 all change term vcc in vdd pp.1 6 introduced iopk+ and iopk - values all introduced 2edl05n06pj all introduced 2edl05 i 06pj , 01.06.2016 update maximum ta from 95 o c to 105 o c in table 5 trademarks of infineon technologies ag aurix?, bluemoon?, c166?, canpak?, cipos?, cipurse?, comneon?, econopack?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobridge?, econodual?, econopim?, eicedriver?, eupec?, fcos?, hitfet?, hybrid pack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my - d?, novalithic?, omnitune?, optimos?, origa?, primarion?, primepack?, primestack?, pro - sil?, profet?, rasic?, reversave?, satric?, sieget?, sindrion?, sipmos?, smarti?, smartlewis?, solid flash?, temp fet?, thinq!?, trenchstop?, tricore?, x - gold?, x - pmu?, xmm?, xposys?. other trademarks advance design system? (ads) of agilent technologies, amba?, arm?, multi - ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat - iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvco, llc (visa holdings inc.). epcos? of epcos ag. flexgo? of microsoft corporation. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrotechnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mifare? of nxp. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research in c., omnivision? of omnivision technologies, inc. openwave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbia n software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektronix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments in corporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited . last trademarks update 2010 - 10 - 26
eicedriver? compact 2e dl family final datasheet 4 , 01.06.2016 table of contents 1 overview ................................ ................................ ................................ ................................ ............. 7 2 blockdiagram ................................ ................................ ................................ ................................ ...... 9 3 pin configur ation, description, and functionality ................................ ................................ ......... 10 3.1 pin configuration and description ................................ ................................ ................................ ...... 10 3.2 low side and high side control pins (lin, hin) ................................ ................................ ............... 10 3.2.1 input voltage range ................................ ................................ ................................ ............................ 10 3.2.2 switching levels ................................ ................................ ................................ ................................ .. 10 3.2.3 input filter time ................................ ................................ ................................ ................................ .... 11 3.3 vdd and gnd ................................ ................................ ................................ ................................ .... 11 3.4 vb and vs (high side supplies) ................................ ................................ ................................ ........ 11 3.5 lo and ho (low and high side outputs) ................................ ................................ .......................... 11 3.6 undervoltage lockout (uvlo) ................................ ................................ ................................ ............ 12 3.7 bootstrap diode ................................ ................................ ................................ ................................ .. 12 3.8 deadtime and interlock function ................................ ................................ ................................ ......... 12 4 electrical parameters ................................ ................................ ................................ ....................... 13 4.1 absolute maximum ratings ................................ ................................ ................................ ............... 13 4.2 required operation conditions ................................ ................................ ................................ ........... 14 4.3 operating range ................................ ................................ ................................ ................................ 14 4.4 static logic function table ................................ ................................ ................................ ................... 15 4.5 static parameters ................................ ................................ ................................ ............................... 15 4.6 dynamic parameters ................................ ................................ ................................ .......................... 17 5 timi ng diagrams ................................ ................................ ................................ ............................... 18 6 package ................................ ................................ ................................ ................................ ............. 20 6.1 pg - dso - 8 ................................ ................................ ................................ ................................ .......... 20 6.2 pg - dso - 14 ................................ ................................ ................................ ................................ ........ 21
eicedriver? compact 2e dl family final datasheet 5 , 01.06.2016 list of figures figure 1 typical application so8 / so14 package 0.5 a ................................ ................................ .................. 8 figure 2 block diagram for 2 edl05x06py ................................ ................................ ................................ ......... 9 figure 3 pin configuration of 2edl family ................................ ................................ ................................ ....... 10 figure 4 input pin structure ................................ ................................ ................................ ............................... 11 figure 5 input filter timing diagram ................................ ................................ ................................ ................... 11 figure 6 timing of short pulse suppression ................................ ................................ ................................ ..... 18 figure 7 timing of of internal deadtime ................................ ................................ ................................ ............ 18 figure 8 input to output propagation delay times and switching times definition ................................ ............. 18 figure 9 operating areas (igbt uvlo levels) ................................ ................................ ................................ . 19 figure 10 operating areas (mosfet uvlo levels) ................................ ................................ .......................... 19 figure 11 output pulse width timing and matching delay timing diagram for positive logic ............................... 19 figure 12 package drawing ................................ ................................ ................................ ................................ 20 figure 13 pcb reference layout left: reference layout right: detail of footprint ................................ .............. 20 figure 14 package drawing ................................ ................................ ................................ ................................ 21 figure 15 pcb reference layout (according to jedec 1s0p) left: reference layout right: detail of footprint .... 21
eicedriver? compact 2e dl family final datasheet 6 , 01.06.2016 list of tables table 1 members of 2edl family ................................ ................................ ................................ ...................... 7 table 2 pin description ................................ ................................ ................................ ................................ ... 10 tabl e 3 abs. maximum ratings ................................ ................................ ................................ ........................ 13 table 4 required operation conditions ................................ ................................ ................................ .......... 14 table 5 operating range ................................ ................................ ................................ ................................ . 14 tabl e 6 static parameters ................................ ................................ ................................ ............................... 15 table 7 dynamic parameters ................................ ................................ ................................ .......................... 17 table 8 data of reference layout ................................ ................................ ................................ ..................... 20 table 9 data of reference layout ................................ ................................ ................................ ..................... 21
eicedriver? compact 2e dl family final datasheet 7 , 01.06.2016 eicedriver? compact 600 v half bridge gate drive ic 1 overview main features ? thin - film - soi - technology ? maximum blocking voltage +600v ? individual control circuits for both outputs ? filtered d etection of under voltage supply ? all inputs clamped by diodes ? active shut down function ? asymmetric undervoltage lockout thresholds for high side and low side ? qualified according to jedec 1 (high temper ature stress tests for 1000h) for target applications product highlights ? insensitivity of the bridge output to negative transient voltages up to - 50v given by soi - technology ? ultra fast bootstrap diode typical applications ? home appliances ? consumer electronics ? f ans, pumps ? general purpose drives product family table 1 members of 2 ed l family sales name special function output current target transistor typ. ls uvlo - t hresholds bootstrap diode package 2edl 05 i06 p f 2edl05i06pj deadtime, interlock 0.5 a igbt 12.5 v / 11.6 v yes dso - 8 dso - 14 2edl 05i 06 bf C 0.5 a igbt 12.5 v / 11.6 v yes dso - 8 2edl 05 n06p f 2edl05n06pj deadtime, interlock 0.5 a 0.5 a mosfet 9 .1 v / 8. 3 v yes dso - 8 dso - 14 1 j - std - 020 and jesd - 022 pg - dso - 8 pg - dso - 14
eicedriver? compact 2e dl family final datasheet 8 , 01.06.2016 description the 2edl family contains devices, which control power devices like mos - transistors or igbts with a maximum blocking voltage of +600v in half bridge configurations. based on the used soi - technology there is an excellent ruggedness on transient voltages. no parasitic thyristor structures are present in the devi ce. hence, no parasitic latch up may occur at all temperature and voltage conditions. the two independent drivers outputs are controlled at the low - side using two different cmos resp. lsttl compatible signals, down up to 3.3v logic. the device includes an under - volta ge detection unit with hysteresis characteristic which are optimised either for igbt or mosfet . those parts, which are designed for igbt have asymmetric undervoltage lockout levels, which support strongly the integrated ultrafast bootstrap diod e. additionally, the offline gate clamping function provides an inherent protection of the transistors for parasitic turn - on by floating gate conditions, when the ic is not supplied via vdd . figure 1 typical application so8 / so14 package 0.5 a vdd lin ho vs lo gnd to load hin vcc dc - bus - dc - bus 2 edl 05 x 06 yy to opamp / comparator vb vb vcc c pwm _ h pwm _ l gnd + 5 v
eicedriver? compact 2e dl family final datasheet 9 , 01.06.2016 2 blockdiagram figure 2 block d iagram for 2 edl0 5 x06p y
eicedriver? compact 2e dl family final datasheet 10 , 01.06.2016 3 pin c onfiguration , d escription , and functionality 3.1 pin configuration and description figure 3 pin configuration of 2edl family table 2 pin description symbol description vdd low side power supply gnd logic ground hin high side logic input lin low s ide logic input vb high side positive power supply ho high side gate driver output vs high side negative power supply lo low side gate driver output nc not connected 3.2 low side and high side control pins ( lin, hin ) 3.2.1 input voltage range all input pins have the capability to process input voltages up to the supply voltage of the ic. the inputs are therefore internally clamped to vdd and gnd by diodes . an internal pull - down resistor is high ohmic, so that it can keep the ic in a safe state in case of pcb crack. 3.2.2 switching levels the schmitt trigger input threshold is such to guarantee lsttl and cmos compatibility down to 3.3 v controller outputs. the i nput schmitt trigger and noise filter provide beneficial noise rejection to short input pulses according to figure 4 and figure 5 . please note, that the switching levels of the input structures remain constant even though they can accept amplitudes up to the ic supply level. v d d 1 1 4 h i n 2 1 3 3 1 2 4 1 1 l i n 5 1 0 6 9 7 8 g n d l o n c n c 1 8 2 7 3 6 4 5 2 e d l ( s o 8 ) 2 e d l ( 0 . 5 a , s o 1 4 ) 2 e d l ( 2 . 3 a , s o 1 4 ) n c v b h o v s n c v d d 1 1 4 h i n 2 1 3 3 1 2 4 1 1 l i n 5 1 0 6 9 7 8 g n d p g n d l o n c n c e n - / f l t n c v b h o v s n c n c n c v d d v b h i n h o v s l i n g n d l o
eicedriver? compact 2e dl family final datasheet 11 , 01.06.2016 figure 4 input pin structure 3.2.3 input filter time figure 5 input filter timing diagram short pulses are suppressed by means of an input filter . all ic, which have undervoltage lockout (uvlo) thresholds for mosfet , have an input filter ti me of t filin = 75 ns typ. and 150ns max. all ic having uvlo thresholds for igbt ha ve filter times of t filin = 15 0ns min and 200ns typ. 3.3 vdd and gnd vdd is the low side supply and it provides power to both the input logic and the low side output power stage. the i nput logic is referenced to gnd ground as well as the under - voltage detection circuit. output power stage is also referenced to gnd ground. the under voltage lockout circuit enables the device to operate at power on when a typical supply voltage higher than v dd uv+ is present. please see section 3.6 undervoltage lockout for further information. a filter time of typ. 1.8 s 1 helps to suppress noise from the uvlo circuit, so that neg ative going vol tage spikes at the supply pins will avoid parasitic uvlo events. 3.4 vb and v s (high side supplies) vb to vs is the high side supply voltage. the high side circuit can float with respect to gnd following the external high side power device emitter/source voltage. due to the low power consumption, the floating driver stage can be supplied by bootstrap topology connected to vdd . a filter time of typ. 1. 8 s 1 helps to suppress noise from the uvlo ci rcuit, so that negative going voltage spikes at the supply pins will avoid parasitic uvlo events. the under - voltage circuit enables the device to operate at power on when a typical supply voltage higher than v dd uv+ is present. please see section 3.6 undervoltage lockout for further information. details on bootstrap supply section and transient immunity can be found in application note eicedriver? 2edl family: technical description . 3.5 lo and ho (low and high side outputs) low side and high side power outputs are specifically designed for pulse operation such as gate drive f or igbt and mosfet devices. low side output is state tr iggered by the respective input , while high side output is edge tr iggered by the respective input . in particular, after an under voltage condition of th e vbs supply, a new turn - on signal (edge) is necessary to activate the high side output . in contrast, the low side outputs switch to the state of their respective inputs after a n under voltage condition of the vdd supply . the output current specification i o + and i o - is defined in a way, which considers the power transistors miller voltage.this helps to design the gate drive better in terms of the application needs. nevertheless, the devices are also characterised for the value of the pulse short circuit valu e i opk + and i opk C . v z = 5 . 2 5 v i n p u t n o i s e f i l t e r v i h ; v i l i l i n i h i n l i n x h i n x v c c 2 e d l - f a m i l y l i n h i n l i n l o h o l o h i g h l o w t f i l i n t f i l i n a ) b )
eicedriver? compact 2e dl family final datasheet 12 , 01.06.2016 3.6 undervoltage lockout ( uvlo ) two different uvlo options are required for igbt and mosfet. the types 2edl05i06px and 2edl05i06bf are designed to drive igbt. there are higher levels of undervoltage lockout for the low side uvlo than for the high side . this supports an improved start up of the ic, when bootstrapping is used. the thresholds for the low side are typically v dd uv+ = 12.5 v (positive going) and v dd uv C = 11.6 v (negative going). the thresholds for the high side are typically v b s uv+ = 11.6 v (positive going) and v bs uv C = 10.7 v (negative going). the types 2edl05n06px are designed to drive power mosfet. a similar distinction for the high side and low side uvlo threshold as for igbt is not realised here. the ic shuts down all the g ate drivers power outputs, when the supply voltage is below typ. v dd uv - = 8. 3 v (min. / max . = 7.5 v / 9 v) . th e turn - on threshold is typ. v dd uv + = 9 .1 v (min. / max. = 8.3 v / 9. 9 v) 3.7 bootstrap diode an ultra fast bootstrap diode is monolithically integrated for establishing the high side supply. the differential resistor of the diode helps to avoid extremely high inrush currents when charging the bootstrap capacitor initially. 3.8 deadtime and interlock function the ic provides a hardware fixed deadtim e. the deadtime is different for the two mosfet types (2edl05n06px) and for the two igbt types (2edl05i06px). the deadtimes are particularly typ. 380 ns for igbt and typ. 75 ns for mosfet. an additional interlock function prevents the two outputs from bein g activated simultaneously. the part 2edl05i06bf does not have the deadtime feature and also not the interlock function. here, the two outpus can be activated simultaneously . __________________________ _______ 1 not subject of production test, verified by characterisation
eicedriver? compact 2e dl family final datasheet 13 , 01.06.2016 4 electrical parameters 4.1 absolute maximum ratings all voltages are absolute voltages referenced to v gnd - potential unless otherwise specified. ( t a =25c) table 3 abs. maximum ratings parameter symbol min. max. unit high side offset voltage (note 1 ) v s v dd - v bs - 6 600 v high side offset voltage ( t p <500ns , note 1 ) v dd - v bs C C v b v dd C t p <500ns , note 1 ) v dd C C v b vs. v s ) (internally clamped) v bs - 1 20 high side output voltage ( v ho vs. v s ) v ho - 0.5 v b + 0.5 low side supply voltage (internally clamped) v dd - 1 20 low side output voltage ( v lo vs. v gnd ) v lo - 0.5 v gnd + 0.5 input voltage lin,hin v in - 0.5 v dd + 0.5 power dissi pation (to package) ( note 2 ) dso8 dso14 p d C C r th(j - a) C C t j C 150 c storage temperature t s - 40 150 offset voltage slew rate (note 4) d v s /dt C note :the minimum value for esd immunity is 1.0kv (human body model). esd immunity inside pins connected to the low side ( vdd , hin, lin, gnd, lo) and pins connected inside each high side itself (vb, ho, vs) is guaranteed up to 1.5kv (human body model) respectively . note 1 : in case v dd > v b there is an additional power dissipation in the internal bootstrap diode between pins vdd and vb in case of activated bootstrap diode . insensitivity of bridge output to negative transient voltage up to C 50v is not subject to prod uction test C verified by design / characterization. note 2: consistent power dissipation of all outputs . all parameters are inside operating range. note 3 : qualification stress tests cover a max. junction temperature of 150c for 1000 h . note 4 : not subj ect of production test, verified by characterisation .
eicedriver? compact 2e dl family final datasheet 14 , 01.06.2016 4.2 required operation conditions all voltages are absolute voltages referenced to v gnd - potential unless otherwise specified. ( t a = 25c) table 4 required operation conditions parameter symbol min. max. unit high side offset voltage (note 1 ) v b 7 620 v low side supply voltage (internally clamped) v dd 10 2 0 4.3 operating range all voltages are absolute voltages referenced to v gnd - potential unless otherwise specified. ( t a = 25c) table 5 operating range parameter symbol min. max. unit high side floating supply offset voltage v s v dd - v bs - 1 500 v high side floating supply offset voltage ( v b vs. v dd , statically) v b dd - 1.0 500 high side floating supply voltage ( v b vs. v s , note 1) igbt - types v bs 13 17.5 mosfet - types 10 17.5 high side output voltage ( v ho vs. v s ) v ho 10 v bs low side output voltage ( v lo vs. v gnd ) v lo 0 v dd low side supply voltage igbt - types v dd 13 17.5 mosfet - types 10 17.5 logic input voltages lin,hin ( note 2) v in 0 17. 5 pulse width for on or off (note 3) igbt - types t in 0. 8 C C t a - 40 1 05 c thermal coefficient dso8 (junction to top , see section 6 ) dso14 ? th(j - top) C C note 1 : logic operational for v b ( v b vs. v gnd ) > 7. 0v note 2 : all input pins (hin, lin) are internally clamped (see abs. maximum ratings) note 3 : t he input pulse may not be transmitted properly i n case of input pulse width at lin and hin below 0.8 s (igbt types) or 0.3 s (mosfet) respectively
eicedriver? compact 2e dl family final datasheet 15 , 01.06.2016 4.4 static l ogic f unction t able vdd vbs lo ho < v dd uv C x 0 0 15v < v bsuv C lin 0 15v 15v 0 0 15v 15v 0 0 15v 15v lin hin all voltages with reference to gnd 4.5 s tatic p arameters v dd = v bs = 15v unless otherwise specified. ( t a = 25c) table 6 static parameters parameter symbol values unit test condition min. typ. max. high level input voltage v ih 1.7 2.1 2.4 v low level input voltage v il 0.7 0.9 1.1 high level output voltage lo ho v oh C C v dd - 0.45 v b - 0. 45 v dd - 1 v b - 1 i o = - 20 ma lo w level output voltage lo ho v ol C C v gnd + 0.13 v s + 0. 13 v gnd + 0.3 v s + 0. 3 i o = 20 ma v dd supply undervoltage positive going threshold igbt - types v dd uv+ 11.8 12.5 13.2 mosfet types 8.3 9.1 9.9 v bs supply undervoltage positive going threshold igbt - types v bsuv + 10.9 11.6 12. 4 mosfet types 8.3 9.1 9.9 v dd supply undervoltage negative going threshold igbt - types v dd uv C 10.9 11.6 12.4 mosfet types 7.5 8.3 9 v bs supply undervoltage nega tive going threshold igbt - types v bsuv C v dd and v bs supply uvlo hysteresis igbt - types v dd uvh v bsuvh 0.5 0.9 C C i lvs+ C v s = 600v high side leakage current betw. vs and gnd i lvs+ 1 C C t j = 125 c, v s = 600 v quiescent current v bs supply (vb only) i qbs1 C v bs supply (vb only) i qbs2 C 1 not subject of production test, verified by characterisation
eicedriver? compact 2e dl family final datasheet 16 , 01.06.2016 table 6 static parameters parameter symbol values unit test condition min. typ. max. current types quiescent current vdd supply ( vdd only) i q dd 1 C v lin = float. quiescent current vdd supply ( vdd only) i q dd 2 C v lin = 3.3 v, v hin =0 quiescent current vdd supply ( vdd only) i q dd 3 C v lin =0 , v hin =3.3 v input bias current i lin+ 15 35 60 a v lin = 3.3 v input bias current i lin C C C v lin = 0 input bias current i h in+ 15 35 60 v h in = 3.3 v input bias current i h in C C C v h in = 0 mean output current for load capacity charging in range from 3 v (20%) to 6 v (40%) i o+ 0.1 8 0.23 C l = 22 nf peak output current turn on (single pulse) i opk+ 1 C C l = 0 ? t p <10 s mean output current for load capacity discharging in range from 12 v (80%) to 9 v (60%) i o C 0. 39 0. 48 C l = 22 nf peak output current turn off (single pulse) i opk C 1 C C r l = 0 ? t p <10 s bootstrap diode forward voltag e between vdd and vb v f,bsd C i f = 0. 3 m a bootstrap diode forward current between vdd and vb i f,bsd 30 55 80 ma v dd C v b = 4 v bootstrap diode resistance r bsd 20 36 54 ? v f 1 = 4 v, v f 2 = 5 v 1 not subject of production test, verified by characterisation
eicedriver? compact 2e dl family final datasheet 17 , 01.06.2016 4.6 dynamic parameters v dd = v bs = 15 v , v s = v gnd , c l = 180 pf unless otherwise specified. ( t a =25c) table 7 dynamic parameters parameter symbol values unit test condition min. typ. max. turn - on propagation delay igbt types t on 280 420 610 ns v lin/hin = 0 or 3.3 v mosfet types 210 310 460 turn - off propagation delay igbt types t off 2 6 0 400 590 mosfet types 2 0 0 30 0 4 4 0 turn - on rise time t r C v lin/hin = 0 or 3.3 v c l = 1 nf turn - off fall time t f C t filin 120 192 C v lin/hin = 0 & 3.3 v mosfet types hin lin 50 100 10 0 150 1 7 0 250 dead time (not for 2edl05i06bf) igbt types dt 260 380 540 ns v lin/hin = 0 & 3.3 v mosfet types 30 75 140 dead time matching abs(dt_lh C mdt C mt on C mt off C in - pw out igbt types pm C in > 1 s mosfet types C
eicedriver? compact 2e dl family final datasheet 18 , 01.06.2016 5 timing diagrams figure 6 timing of short pulse suppression figure 7 timing of of internal deadtime figure 8 input to output propagation delay times and switching times definition l i n 1 , 2 , 3 h i n 1 , 2 , 3 h o 1 , 2 , 3 l o 1 , 2 , 3 1 2 v 3 v 3 v 1 2 v 1 . 6 5 v 1 . 6 5 v d t d t l i n h i n h o l o 1 . 6 5 v 1 . 6 5 v 8 0 % 2 0 % 2 0 % 8 0 % p w o u t t o n t o f f t r t f p w i n h i n / l i n h i n / l i n h o / l o h o / l o l o w t i n < t f i l i n t i n t i n > t f i l i n t f i l i n t i n h i n / l i n h i n / l i n h o / l o h o / l o h i g h t f i l i n t i n < t f i l i n t i n t i n > t f i l i n t i n
eicedriver? compact 2e dl family final datasheet 19 , 01.06.2016 figure 9 operating areas ( igbt uvlo levels ) figure 10 operating a reas ( mosfet uvlo levels ) figure 11 output pulse width timing and matching delay timing diagram for positive logic h i n / l i n h o / l o p w i n p w o u t m t o n p m = p w i n - p w o u t h i n / l i n p w i n h o / l o m t o f f p m = p w i n - p w o u t p w o u t
eicedriver? compact 2e dl family final datasheet 20 , 01.06.2016 6 package 6.1 pg - dso - 8 max. reflow solder temperature: 265c acc. jedec max. wave solder temperature: 245c acc. jedec figure 12 package drawing figure 13 pcb reference layout left: reference layout right: detail of footprint the thermal coefficient is used to calculate the junction temperature, when the ic surface temperature is measured. the junction temperature is ? j = th(j - top) ? ? ? + ? top table 8 data of reference layout dimensions material metal (copper) 76.2 ? ? ? therm = 0.3 w/mk) 70m ( ? therm = 388 w/mk)
eicedriver? compact 2e dl family final datasheet 21 , 01.06.2016 6.2 pg - dso - 14 max. reflow solder temperature: 265c acc. jedec max. wave solder temperature: 245c acc. jedec figure 14 package drawing figure 15 pcb reference layout (according to jedec 1s0p) left: reference layout right: detail of footprint the thermal coefficient is used to calculate the junction temperature, when the ic surface temperature is measured. the junction temperature is ? j = th(j - top) ? ? ? + ? top table 9 data of reference layout dimensions material metal (copper) 76.2 ? ? ? therm = 0.3 w/mk) 70m ( ? therm = 388 w/mk)
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